The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A resistive random access memory (RRAM) array includes RRAM cells arranged at intersections of word lines and bitlines. A RRAM cell includes an insulating material (e.g., a dielectric) as a resistive element. The resistance of the insulating material increases when current is passed through the insulating material in one direction and decreases when current is passed through the insulating material in an opposite direction. Accordingly, the RRAM cell can be programmed to a high resistance state by passing current through the RRAM cell in one direction and a low resistance state by passing current through the RRAM cell in an opposite direction. The high resistance state can be used to denote logic high (binary 1), and the low resistance state can be used to denote logic low (binary 0), or vice versa. Once written, read operation can be performed using either direction of current flow.
FIG. 1 shows an example of a memory 100 including a plurality of RRAM memory cells 102-1, 102-2, . . . and 102-R (collectively RRAM memory cells 102), where R is an integer greater than one. The RRAM memory cells 102 in FIG. 1 are located along a bitline. Each of the RRAM memory cells 102-1, 102-2, . . . and 102-R includes a transistor T1, T2, . . . TR and an RRAM element represented by resistors RRRAM—1, RRRAM—2, . . . , and RRRAM—R, respectively.
One end of the RRAM elements RRRAM—1, RRRAM—2, . . . , and RRRAM—R is connected to first terminals of the transistors T1, T2, . . . TR. Another end of the RRAM elements RRRAM—1, RRRAM—2, . . . , and RRRAM—R is connected to a first bitline terminal BLP. Second terminals of the transistors T1, T2, . . . TR are connected to a second bitline terminal BLN, which may be a ground reference. Gates of the transistors T1, T2, . . . TR are connected to wordlines WL1, WL2, . . . , WLR, respectively.
As can be appreciated, the memory 100 may include additional columns and rows of RRAM memory cells 102. Additional bitline terminals BLP and BLN may be connected to the other columns of RRAM memory cells (not shown) in a similar manner. The wordlines WL1, WL2, . . . , WLR may be connected to the RRAM memory cells 102 arranged in the same row.
The RRAM memory cell 102 may be read by asserting the wordline and driving either positive and negative current or voltage on the first bitline terminal BLP. The voltage or current is compared to one or more thresholds to identify a state of the RRAM memory cell. The RRAM elements may be damaged when the read or write current or voltage is too high.